Solid state lighting dies with quantum emitters and associated methods of manufacturing

ABSTRACT

Solid state lighting dies and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting die includes a substrate material, a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The second semiconductor material has a surface facing away from the substrate material. The solid state lighting die also includes a plurality of openings extending from the surface of the second semiconductor material toward the substrate material.

TECHNICAL FIELD

The present technology is directed generally to solid state lighting(“SSL”) devices with quantum emitters and associated methods ofmanufacturing.

BACKGROUND

SSL devices generally use semiconductor light emitting diodes (“LEDs”),organic light emitting diodes (“OLEDs”), laser diodes (“LDs”), and/orpolymer light emitting diodes (“PLEDs”) as sources of illuminationrather than electrical filaments, a plasma, or a gas. FIG. 1 is across-sectional diagram of a portion of a conventional indium-galliumnitride (“InGaN”) LED die 10. As shown in FIG. 1, the LED die 10includes a substrate 12 (e.g., silicon carbide, sapphire, or silicon),an N-type gallium nitride (“GaN”) material 14, an active region 16(e.g., GaN/InGaN multi quantum wells (“MQWs”)), and a P-type GaNmaterial 18 on top of one another in series. The LED die 10 can alsoinclude a first contact 11 on the P-type GaN material 18 and a secondcontact 15 on the N-type GaN material 14.

The GaN/InGaN materials of the LED die 10 are generally formed viaepitaxial growth and typically include a large number of crystal defectsthat can negatively impact the optical and/or electrical performance ofthe LED die 10. For example, FIG. 2 is a transmission electronmicroscopy (“TEM”) image 20 of a GaN layer 24 formed on a sapphiresubstrate 22 via metal organic chemical vapor deposition (“MOCVD”). Asshown in FIG. 2, the GaN layer 24 includes a plurality of threadingdislocations 26 extending away from the substrate 22 into the GaN layer24. It is believed that the threading dislocations 26 and/or othercrystal defects can negatively impact the performance of LEDs.Accordingly, several improvements to reduce the negative impact ofcrystal defects in LEDs may be desirable.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a portion of an LED die inaccordance with the prior art.

FIG. 2 is a TEM image of a portion of an LED die in accordance with theprior art.

FIGS. 3A-3L are cross-sectional and top views of a portion of amicroelectronic substrate undergoing a process for forming an SSL die inaccordance with embodiments of the technology.

FIGS. 4A-4D are cross-sectional and top views of a portion of amicroelectronic substrate undergoing another process for forming an SSLdie in accordance with embodiments of the technology.

FIGS. 5A-5F are cross-sectional views of a portion of a microelectronicsubstrate undergoing another process for forming an SSL die inaccordance with embodiments of the technology.

FIG. 6A is a cross-sectional view of a portion of a microelectronicsubstrate 100 during a processing stage for forming a plurality of SSLdies 200 in accordance with embodiments of the technology

FIG. 6B is a cross-sectional view of an SSL device incorporating an SSLdie with quantum emitters in accordance with embodiments of thetechnology.

DETAILED DESCRIPTION

Various embodiments of SSL devices and dies with quantum emitters andassociated methods of manufacturing are described below. The term“microelectronic substrate” is used throughout to include substratesupon which and/or in which SSL dies, microelectronic devices,micromechanical devices, data storage elements, read/write components,and other features are fabricated. The term “lattice dislocation”generally refers to a crystallographic defect or irregularity within acrystal structure. A lattice dislocation can include an edgedislocation, a threading (or screw) dislocation, a V-defect, and/or acombination thereof. A person skilled in the relevant art will alsounderstand that the technology may have additional embodiments, and thatthe technology may be practiced without several of the details of theembodiments described below with reference to FIGS. 3A-6B.

FIGS. 3A-3L are cross-sectional and top views of a portion of amicroelectronic substrate 100 undergoing a process for forming an SSLdie in accordance with embodiments of the technology. The SSL die can bean LED, an OLED, a LD, a PLED, and/or other suitable devices. In thefollowing description, common acts and structures are identified by thesame reference numbers. Even though only particular processingoperations and associated structures are illustrated in FIGS. 3A-3L, incertain embodiments, the process can also include forming a lens, amirror material, support structures, conductive interconnects, and/orother suitable mechanical/electrical components (not shown).

As shown in FIG. 3A, an initial operation of the process can includeforming an SSL structure 101 and an optional buffer material 103 on asubstrate material 102. The substrate material 102 can include a silicon(Si) wafer (e.g., with a Si(1,1,1) crystal orientation), aluminumgallium nitride (AlGaN), GaN, silicon carbide (SiC), sapphire (Al₂O₃), acombination of the foregoing materials, and/or other suitable substratematerials. In certain embodiments, the optional buffer material 103 caninclude aluminum nitride (AlN), GaN, zinc nitride (ZnN), and/or othersuitable materials. In other embodiments, the optional buffer material103 may be omitted, and the SSL structure 101 may be formed directly onthe substrate material 102. In further embodiments, other suitablematerials (e.g., zinc oxide (ZnO₂)) may be formed on the substratematerial 102 in addition to or in lieu of the buffer material 103.

The SSL structure 101 can include a first semiconductor material 104, anactive region 106, and a second semiconductor material 108 stacked oneon the other. In one embodiment, the first and second semiconductormaterials 104 and 108 include an N-type GaN material and a P-type GaNmaterial, respectively. In another embodiment, the first and secondsemiconductor materials 104 and 108 include a P-type GaN material and anN-type GaN material, respectively. In further embodiments, the first andsecond semiconductor materials 104 and 108 can individually include atleast one of gallium arsenide (GaAs), aluminum gallium arsenide(AlGaAs), gallium arsenide phosphide (GaAsP), gallium(III) phosphide(GaP), zinc selenide (ZnSe), boron nitride (BN), AlGaN, and/or othersuitable semiconductor materials.

The active region 106 can include a single quantum well (“SQW”), MQWs,and/or a bulk semiconductor material. As used hereinafter, a “bulksemiconductor material” generally refers to a single grain semiconductormaterial (e.g., InGaN) with a thickness greater than about 10 nanometersand up to about 500 nanometers. In certain embodiments, the activeregion 106 can include an InGaN SQW, InGaN/GaN MQWs, and/or an InGaNbulk material. In other embodiments, the active region 116 can includealuminum gallium indium phosphide (AlGaInP), aluminum gallium indiumnitride (AlGaInN), and/or other suitable materials or configurations.

The SSL structure 101 and the optional buffer material 103 can be formedon the substrate 102 via MOCVD, molecular beam epitaxy (“MBE”), liquidphase epitaxy (“LPE”), hydride vapor phase epitaxy (“HVPE”), and/orother suitable epitaxial growth techniques. It has been observed,however, that the SSL structure 101 formed via the foregoing techniquestypically includes a high density of lattice dislocations. For example,as shown in FIG. 3A, the SSL structure 101 can include an indentationdefect 111 (commonly referred to as a “V-defect” due to its V-shapedcross-section) and a threading dislocation 113 laterally spaced apartfrom each other. Only one indentation defect 111 and one threadingdislocation 113 are illustrated in FIG. 3A for illustration purposes. Itis understood that the SSL structure 101 can include a plurality ofindentations, threading dislocations, and/or other lattice dislocations(not shown).

The indentation defect 111 can include sidewalls 111 a and 111 b thatextend at least partially into the SSL structure 101. In the illustratedembodiment, the sidewalls 111 a and 111 b extend from a semiconductorsurface 108 a of the second semiconductor material 108 into the firstsemiconductor material 104 and the active region 106. In otherembodiments, the sidewalls 111 a and 111 b can extend into the activeregion 106 without extending into the first semiconductor material 104.In further embodiments, the sidewalls 111 a and 111 b can extend intothe optional buffer material 103, and/or into the substrate material102.

The threading dislocation 113 can extend at least partially between theoptional buffer material 103 and the second semiconductor material 108.In the illustrated embodiment, the threading dislocation 113 isgenerally perpendicular to a buffer surface 103 a of the optional buffermaterial 103. The threading dislocation 113 also extends the entirethickness between the buffer surface 103 a and the semiconductor surface108 a. In other embodiments, the threading dislocation 113 may extendonly partially between the buffer surface 103 a and the semiconductorsurface 108 a. In further embodiments, the threading dislocation 113 mayextend at an angle of other than 90° with respect to the buffer surface103 a. In yet further embodiments, the threading dislocation 113 may bejoined (e.g., vertically) with the indentation defect 111 and/or mayhave other structures and/or configurations.

Without being bound by theory, it is believed that the indentationdefect 111 and the threading dislocation 113 can negatively impact theoptical and/or electrical performance of the SSL structure 101. Forexample, it is believed that the threading dislocation 113 can shortcircuit the active region 106 and/or cause current leakage in the SSLstructure 101. It is also believed that impurities (e.g., carbon (C),oxygen (O), silicon (Si), and hydrogen (H)) tend to aggregate in thecores of the threading dislocation 113. Such impurities can causenon-radiated hole-electron recombination during operation, thus causinglow optical efficiencies in the SSL structure 101. It is furtherbelieved that the indentation defect 111 can form carrier pathways thatshort circuit the SSL structure 101 when a conductive material (notshown) is formed on the second semiconductor material 108 as anelectrical contact.

Several embodiments of the process can reduce or eliminate the negativeimpact of the indentation defect 111, the threading dislocation 113,and/or other lattice dislocations by forming a plurality of individualemitters on the SSL structure 101. FIG. 3B is a cross-sectional view andFIG. 3C is a top view of the microelectronic substrate 100 during anoperation of the process. As shown in FIGS. 3B and 3C, a maskingmaterial 110 (e.g., a photoresist) can be formed on the semiconductorsurface 108 a of the second semiconductor material 108. The maskingmaterial 110 can then be patterned to define a plurality of maskopenings 112 via photolithography and/or other suitable techniques. Themask openings 112 individually expose a portion of the semiconductorsurface 108 a.

FIG. 3D is a cross-sectional view and FIG. 3E is a top view of themicroelectronic substrate 100 during a subsequent operation of theprocess. As shown in FIGS. 3D and 3E, portions of the SSL structure 101can be removed via the mask openings 112 in the masking material 110 toform a plurality of emitters 116 separated from one another bycorresponding SSL openings 114. Suitable techniques for removingmaterials from the SSL structure 101 can include wet etching, dryetching, laser ablation, and/or other suitable techniques. In theillustrated embodiment, the SSL structure 101 is etched down into thefirst semiconductor material 104. In other embodiments, as shown in FIG.3F, etching the SSL structure 101 may stop at a top surface 104 a of thefirst semiconductor material 104. In further embodiments, the SSLstructure 101 may be etched down into the optional buffer material 103(as shown in FIG. 3G), and/or into the substrate material 102 (as shownin FIG. 3H).

FIG. 3I is a cross-sectional view and FIG. 3J is a top view of themicroelectronic substrate 100 during another operation of the process.As shown in FIGS. 3I and 3J, the masking material 110 (FIGS. 3D-3H) canbe removed from the semiconductor surface 108 a of the secondsemiconductor material 108 via wet etching, dry etching, and/or othersuitable techniques. As shown in FIGS. 3I and 3J, the emitters 116(identified individually first to fourth emitter 116 a-116 d,respectively, in FIG. 3I) can be arranged as an array (e.g., as athree-by-four array in FIG. 3J for illustration purposes). In otherembodiments, the emitters 116 may be arranged radially in a circularpattern, in a semicircular pattern, and/or other suitable patterns (notshown). In further embodiments, the emitters 116 may be arranged in acombination of different arrays and/or patterns. In yet furtherembodiments, the emitters 116 may be arranged randomly on themicroelectronic substrate 100.

The emitters 116 can individually include an active element 106′ definedby the remaining portions of the active region 106 at the emitters 116,a second semiconductor element 108′ defined by the remaining portions ofthe second semiconductor material 108 at the emitters 116, andoptionally a first semiconductor element 104′ defined by the remainingportions of the first semiconductor material 104. As such, in theillustrated embodiment, the emitters 116 individually include a firstsemiconductor element 104′, an active element 106′, and a secondsemiconductor element 108′ that together form an SSL element 101′. Inother embodiments, the emitters 116 can also include a portion of thebuffer material 103 and/or the substrate material 102.

In certain embodiments, the emitters 116 can have generally similarshape, size, composition of material, and/or other suitablecharacteristics. For example, in the illustrated embodiment, theemitters 116 have a generally rectangular cross section with a length L(e.g., about 10 nanometers to about 50 nanometers) and a width W (e.g.,about 10 nanometers to about 50 nanometers). The emitters 116 can alsohave a generally similar height H (e.g., about 50 nanometers to about500 nanometers). The individual emitters 116 can include an N-type GaNfirst semiconductor element 104′, InGaN MQWs, and a P-type GaN secondsemiconductor element 108′. In other embodiments, at least one of thelength L, the width W, and the height H of at least one of the emitters116 may have other suitable values different than other emitters 116. Infurther embodiments, at least one of the first semiconductor element104′, the active element 106′, and the second semiconductor element 108′may have other suitable materials and/or configurations.

Without being bound by theory, it is believed that the emitters 116 withthe foregoing dimensions have conducting characteristics that areclosely related to the size and shape of the individual emitters 116.Generally, it is believed that emitters 116 with smaller sizes (e.g.,cross-sectional area) have larger bandgaps. As a result, more energy isneeded to excite electrons in the emitters 116 from a covalent bond to aconduction band. More energy is also released when the excited electronsreturn to the covalent bond from the conduction band. Thus, smalleremitters 116 can produce electromagnetic radiation in the visiblespectrum at higher frequencies than larger emitters 116, resulting in acolor shift from red to blue, which is commonly referred to as a “blueshift.”

It is believed that the foregoing size dependency of emissioncharacteristics is due at least in part to quantum confinement. Withoutbeing bound by theory, it is believed that the bandgap in a bulkmaterial (e.g., with dimensions greater than about 100 nanometers) canbe considered as having a fixed value because the dimensions of the bulkmaterial are much larger than the average physical separation (commonlyreferred to as the “Bohr radius”) between an excited electron and thecorresponding hole (commonly referred to as “exciton”). However, whenthe size of the emitters 116 is sufficiently small (e.g., approaching orequal to the Bohr radius), the electron energy levels in the emitters116 can no longer be considered continuous, but are instead discrete.The discrete energy levels thus limit the possible energy states thatthe electrons may be in, resulting in higher bandgap energies than inbulk materials.

Accordingly, the emission characteristics (e.g., peak emissionfrequencies) of the individual emitters 116 may be controlled byadjusting at least one of a size (e.g., the length L, the width W, theheight H, and/or other suitable cross-sectional dimensions), a shape(e.g., a cross-sectional shape), a composition of the active element106′ (e.g., an indium percentage in InGaN SQW, MQWs, or a bulkmaterial), and a configuration of the active element 106′ (e.g., athickness of material sub-layers in InGaN SQW, MQWs). For example, thecross-sectional size of the emitters 116 may be controlled by adjustingthe size of the SSL openings 114. In another example, the compositionand/or the configuration of the active element 106′ may be controlled byadjusting at least one of a partial pressure of an indium precursor, adeposition temperature, and/or other suitable deposition parametersduring MOCVD.

In certain embodiments, the SSL die may include emitters 116 configuredto emit at different peak emission frequencies such that a combinationof all the emissions produces a desired color appearance (e.g., white,blue, purple, etc.). For example, in one embodiment, the emitters 116can include a first group and a second group of emitters 116. The firstgroup can be configured to emit at a first peak frequency, and thesecond group can be configured to emit at a second peak frequency byhaving different size, shape, composition and/or configuration of theactive element 106′, and/or other suitable characteristics. Whencombined, the emissions from the first and second groups can appearwhite or another desired color to an average observer. In otherembodiments, the emitters 116 can include three, four, or any desirednumber of groups that are configured to emit at different peakfrequencies.

FIGS. 3K and 3L are cross-sectional views of the microelectronicsubstrate 100 during another operation of the process, in which aconductive material 120 is formed on the SSL structure 101. In certainembodiments, the conductive material 120 can include indium tin oxide(“ITO”), aluminum zinc oxide (“AZO”), fluorine-doped tin oxide (“FTO”),and/or other suitable transparent conductive oxide (“TCOs”). In otherembodiments, the conductive material 120 can include copper (Cu),aluminum (Al), silver (Ag), gold (Au), platinum (Pt), and/or othersuitable metals. In further embodiments, the conductive material 120 caninclude a combination of TCOs and one or more metals. Techniques forforming the conductive material 120 can include MOCVD, MBE, spraypyrolysis, pulsed laser deposition, sputtering, electroplating, and/orother suitable deposition techniques.

In certain embodiments, as shown in FIG. 3K, the process can includesubstantially filling the SSL openings 114 with an insulating material118 and subsequently forming the conductive material 120 on thesemiconductor surface 108 a of the second semiconductor material 108 andthe insulating material 118. The insulating material 118 can includesilicon dioxide (SiO₂), silicon nitride (SiN), hafnium silicate(HfSiO₄), zirconium silicate (ZrSiO₄), hafnium dioxide (HfO₂), zirconiumdioxide (ZrO₂), aluminum oxide (Al₂O₃), and/or other suitabletransparent materials with a dielectric constant higher than about 1.0at 20° C. under 1 kHz. Techniques for forming the insulating material118 can include chemical vapor deposition (“CVD”), atomic layerdeposition (“ALD”), spin-on coating, thermal oxidation, and/or othersuitable techniques.

In other embodiments, as shown in FIG. 3L, the insulating material 118can generally conform to the neighboring emitters 116 withoutsubstantially filling the SSL openings 114. As a result, the conductivematerial 120 includes a first conductive portion 120 a on thesemiconductor surface 108 a of the second semiconductor material 108 anda second portion 120 b in the SSL openings 114. In further embodiments,the conductive material 120 and/or the insulating material 118 may haveother suitable configurations.

The SSL die formed in accordance with several embodiments of theforegoing process can at least reduce the density of latticedislocations relative to the whole surface area of the SSL structure 101when compared to conventional devices. For example, as shown in FIGS.3B, 3D, and 31, at least a portion of the indentation defect 111 can beremoved from the SSL structure 101 when portions of the SSL structure101 are removed from the SSL structure 101. In other embodiments, atleast a portion of the threading dislocation 113 and/or other crystaldislocations may also be removed. As a result, the SSL structure 101 mayhave a lower density of lattice dislocations than conventional devices.

The SSL die formed in accordance with several embodiments of theforegoing process can also localize the negative impact of threadingdislocations and/or other lattice dislocations. In conventional devices,threading dislocations can affect a large portion of an SSL structure byreducing the current density passing therethrough or completely shortcircuiting the SSL structure. In contrast, in the SSL structure 101formed in accordance with several embodiments of the foregoing process,such an effect is at least reduced. For example, as shown in FIGS. 3Kand 3L, when an electrical voltage is applied across the individualemitters 116, the threading dislocation 113 associated with the thirdemitter 116 c may reduce a current density in or short circuit the thirdemitter 116 c. However, the threading dislocation 113 does not affectthe first, second, or fourth emitters 116 a, 116 b, and 116 d becausethe third emitter 116 c and the threading dislocation 113 areelectrically insulated from the other emitters 116. As a result, thenegative impact of the threading dislocation 113 may be localized.

The SSL die formed in accordance with several embodiments of theforegoing process can also have higher optical efficiencies whencompared to conventional devices. As shown in FIGS. 3K and 3L, theindividual emitters 116 have a three dimensional configuration insteadof a two dimensional configuration, as in conventional devices. As aresult, the individual emitters 116 have a reduced planar top surfacearea when compared to conventional devices. Thus, more light may escapefrom the emitters 116 by forming angles greater than an angle ofinternal reflection with the sides of the emitters 116.

FIGS. 4A-4D are cross-sectional and top views of a portion of themicroelectronic substrate 100 undergoing another process for forming anSSL die in accordance with the embodiments of the technology. In thefollowing description, certain operations of the process and structuresof the SSL die can be generally similar to those discussed above withreference to FIGS. 3A-3I. As such, only significant differences aredescribed below.

FIG. 4A is a cross-sectional view and FIG. 4B is a top view of themicroelectronic substrate 100 during an initial operation of theprocess. As shown in FIGS. 4A and 4B, a shielding material 210 is formedon the buffer surface 103 a of the optional buffer material 103.Portions of the shielding material 210 are removed to form a pluralityof shielding openings 212. In the illustrated embodiment, the shieldingopenings 212 are arranged as an array on the microelectronic substrate100. In other embodiments, the shielding openings 212 can also bearranged in a circular, semi-circular, and/or other suitable patterns.In further embodiments, the shielding openings 212 may be arrangedrandomly on the microelectronic substrate 100.

In certain embodiments, the shielding material 210 can include aphotoresist that may be patterned via photolithography. In otherembodiments, the shielding material 210 can include silicon dioxide(SiO₂), silicon nitride (SiN), and/or other suitable materials. Formingthe shielding openings 212 can include depositing a photoresist (notshown) onto the shielding material 210, patterning the photoresist, andpartially removing the shielding material 210 to form the shieldingopenings 212 via wet etch, dry etch, or other suitable techniques. Infurther embodiments, the shielding material 210 may include othersuitable materials.

FIG. 4C shows another operation of the process, in which the firstsemiconductor material 104, the active region 106, and the secondsemiconductor material 108 are formed on the optional buffer material103 via the shielding openings 212 in the shielding material 210.Without being bound by theory, it is believed that the first and secondsemiconductor materials 104 and 108 and the active region 106 canpreferentially grow on the optional buffer material 103 because theforegoing materials 104, 106, and 108 would not readily nucleate on theshielding material 210. As a result a plurality of emitters 116 with afirst semiconductor element 104′, an active element 106′, and a secondsemiconductor element 108′ can be formed on the microelectronicsubstrate 100 via the shielding openings 212.

Even though the shielding material 210 is shown in FIGS. 4A-4C as beingformed on the optional buffer material 103 before forming the SSLstructure 101, FIG. 4D shows another embodiment in which the shieldingmaterial 210 is formed on the first semiconductor material 104 beforethe active region 106 and the second semiconductor material 108 areformed. As a result, the individual emitters 116 of this alternativeembodiment can also include a portion of the first semiconductormaterial 104, the active element 106′, and the second semiconductorelement 108′. In any of the foregoing embodiments, after forming theemitters 116, the shielding material 210 may be removed from themicroelectronic substrate 100. Subsequently, the conductive material 120(shown in FIGS. 3K and 3L) may be formed on the SSL structure 101, asdiscussed in detail with reference to FIGS. 3K and 3L.

FIGS. 5A-5E are cross-sectional views of a portion of a microelectronicsubstrate 100 undergoing another process for forming an SSL die inaccordance with embodiments of the technology. As shown in FIG. 5A, aninitial operation of the process can include forming a photoresist 220on the buffer surface 103 a of the optional buffer material 103 andsubsequently patterned to form the plurality of shielding openings 212via photolithography.

As shown in FIG. 5B, a subsequent operation of the process can includeremoving at least a portion of the optional buffer material 103 throughthe shielding openings 212 to form indentations 216. Techniques forremoving the optional buffer material 103 can include wet etching, dryetching, and/or other suitable material removal techniques. In theillustrated embodiments, the optional buffer material 103 is partiallyremoved through the shielding openings 212. In other embodiments, theoptional buffer material 103 can be completely removed through theshielding openings 212. In further embodiments, the optional buffermaterial 103 may be completely removed along with underlying materials,for example, the substrate material 102 through the shielding openings212.

As shown in FIG. 5C, another operation of the process can includedepositing an insulating material 218 into the indentations 216. Theinsulating material 218 can include silicon dioxide (SiO₂), siliconnitride (SiN), and/or other suitable insulating materials. In theillustrated embodiment the deposited insulating material 218 isgenerally coplanar with the buffer surface 103 a of the buffer material103. In other embodiments, the insulating material 218 may be offsetfrom the buffer surface 103 a of the optional buffer material 103. Infurther embodiments in which the buffer material 103 is omitted, theindentations 216 and the insulating material 218 may be formed in thesubstrate material 102.

As shown in FIG. 5D, a subsequent operation of the process includesremoving the photoresist 220 from the microelectronic substrate 100. Asshown in FIG. 5E, the SSL structure 101 having the first semiconductormaterial 104, the active region 106, and the second semiconductormaterial 108 can be formed on the optional buffer material 103. Withoutbeing bound by theory, it is believed that the first and secondsemiconductor materials 104 and 108 and the active region 106 canpreferentially form on the optional buffer material 103 because theforegoing materials 104, 106, and 108 would not readily nucleate on theinsulating material 218. As a result, the plurality of emitters 116 withindividual first semiconductor element 104′, active element 106′, andsecond semiconductor element 108′ can be formed on the microelectronicsubstrate 100 via the shielding openings 212.

Even though the insulating material 218 is shown above as formed in theoptional buffer material 103, the insulating material 218 can also beformed in the first semiconductor material 104 prior to forming theactive region 106 and the second semiconductor material 108 (FIG. 5).After forming the emitters 116, the process can include forming theconductive material 120 (shown in FIGS. 3K and 3L) on the SSL structure101, as discussed above with reference to FIGS. 3K and 3L.

In the embodiments discussed above with reference to FIGS. 3A-5F, onlyone SSL die is formed in the microelectronic substrate 100. In otherembodiments, a plurality of SSL dies may be formed in themicroelectronic substrate 100 at the same time following generallysimilar processing stages. FIG. 6A is a cross-sectional view of aportion of a microelectronic substrate 100 during a processing stage forforming a plurality of SSL dies 200 in accordance with embodiments ofthe technology. In the illustrated embodiment, a plurality of SSL dies200 (identified individually as first and second SSL dies 200 a and 200b, respectively) are formed in the microelectronic substrate 100. Eventhough only two SSL dies 200 are illustrated in FIG. 6A, in otherembodiments, three, four, or any other desired number of SSL dies 200may be formed in the microelectronic substrate 100.

As shown in FIG. 6A, a gap 115 separates the first and second SSL dies200 a and 200 b, which are generally similar to the SSL die discussedabove with reference to FIG. 3K. In other embodiments, the SSL dies 200a and 200 b can individually have structures and functions generallysimilar to other embodiments of the SSL die discussed above withreference to FIGS. 3A-5F. The first and second SSL dies 200 a and 200 bmay be formed simultaneously or formed in sequence. In certainembodiments, the gap 115 may be formed by etching, laser ablation, sawcutting, and/or other suitable techniques subsequent to forming thefirst and second SSL dies 200 a and 200 b. In other embodiments, the gap115 may be formed via other suitable techniques. Subsequent to formingthe SSL dies 200, the individual SSL dies 200 may be singulated alongthe gap 115. The singulated SSL dies 200 can be assembled into an SSLdevice, an example of which is discussed below with reference to FIG.6B.

FIG. 6B is a cross-sectional view of an SSL device 300 incorporating anSSL die 200 with quantum emitters in accordance with embodiments of thetechnology. As shown in FIG. 6B, the SSL device 300 can include asupport structure 302 holding the SSL die 200 and a converter material304 disposed on the SSL die 200. The SSL die 200 can have structures andfunctions generally similar to any of the embodiments discussed abovewith reference to FIGS. 3A-5F.

The support structure 302 can include any suitable structure forcarrying and/or otherwise holding the SSL die 200 and the convertermaterial 304. In certain embodiments, the support structure 302 can beconstructed from silicon (Si), gallium nitride (GaN), aluminum nitride(AlN), and/or other suitable semiconductor materials. In otherembodiments, the support structure 302 can be constructed from copper(Cu), aluminum (Al), tungsten (W), stainless steel, and/or othersuitable metal and/or metal alloys. In further embodiments, the supportstructure 302 can be constructed from diamond, glass, quartz, siliconcarbide (SiC), aluminum oxide (Al₂O₃), and/or other suitable crystallineor ceramic materials.

The converter material 304 can be configured to emit at a desiredwavelength under stimulation such that a combination of the emissionfrom the SSL die 200 and from the converter material 304 can emulate atarget color (e.g., white light). For example, in one embodiment, theconverter material 304 can include a phosphor containingcerium(III)-doped yttrium aluminum garnet (YAG) at a particularconcentration for emitting a range of colors from green to yellow and tored under photoluminescence. In other embodiments, the convertermaterial 304 can include neodymium-doped YAG, neodymium-chromiumdouble-doped YAG, erbium-doped YAG, ytterbium-doped YAG,neodymium-cerium double-doped YAG, holmium-chromium-thulium triple-dopedYAG, thulium-doped YAG, chromium(IV)-doped YAG, dysprosium-doped YAG,samarium-doped YAG, terbium-doped YAG, and/or other suitable phosphorcompositions. In yet other embodiments, the converter material 106 caninclude europium phosphors (e.g., CaS:Eu, CaAlSiN₃:Eu, Sr₂Si₅N₈:Eu,SrS:Eu, Ba₂Si₅N₈:Eu, Sr₂SiO₄:Eu, SrSi₂N₂O₂:Eu, SrGa₂S₄:Eu, SrAl₂O₄:Eu,Ba₂SiO₄:Eu, Sr₄All₄O₂₅:Eu, SrSiAl₂O₃N:Eu, BaMgAl₁₀O₁₇:Eu, Sr₂P₂O₇:Eu,BaSO₄:Eu, and/or SrB₄O₇:Eu).

Even though the converter material 304 is shown in FIG. 6B as onlycovering the top surface of the SSL die 200, in other embodiments, theconverter material 304 can also cover side surfaces of the SSL die 200.In further embodiments, the SSL device 300 can also include lenses, wirebonds, and/or other suitable optical, electrical, and/or mechanicalcomponents. In yet further embodiments, the converter material 304 maybe omitted.

From the foregoing, it will be appreciated that specific embodiments ofthe technology have been described herein for purposes of illustration,but that various modifications may be made without deviating from thedisclosure. Many of the elements of one embodiment may be combined withother embodiments in addition to or in lieu of the elements of the otherembodiments. Accordingly, the disclosure is not limited except as by theappended claims.

I/We claim:
 1. A solid state lighting die, comprising: a substratematerial; a plurality of emitters on the substrate material, theindividual emitters including: a first semiconductor element; a secondsemiconductor element spaced apart from the first semiconductor element;an active element directly between the first and second semiconductorelements, the active region including at least one of (a) indium galliumnitride single quantum well, (b) gallium nitride (GaN)/indium galliumnitride (InGaN) multiple quantum wells, and (c) an InGaN bulk material;and an insulating material on the substrate material, the insulatingmaterial having a plurality of portions individually between adjacentemitters.
 2. The solid state lighting die of claim 1 wherein: thesubstrate material includes a silicon wafer having a Si(1,1,1) crystalorientation at a surface; the solid state lighting die further includesa buffer material on the surface of the silicon wafer, the buffermaterial including at least one of aluminum nitride (AlN), galliumnitride (GaN), and zinc nitride (ZnN); the plurality of emitters arearranged in an array; the plurality of emitters are in direct contactwith the buffer material; the plurality of emitters have a generallyrectangular cross section with a length L and a width W; the length L isfrom about 10 nanometers to about 50 nanometers; the width W is fromabout 10 nanometers to about 50 nanometers; the first semiconductorelement includes an N-type GaN material; the second semiconductorelement includes a P-type GaN material; the active element includesGaN/InGaN multiple quantum wells; the second semiconductor element has asemiconductor surface; the insulating material has an insulating surfacegenerally coplanar with the semiconductor surface; and the solid statelighting die further includes a conductive material in direct contactwith both the semiconductor surface and the insulating surface.
 3. Thesolid state lighting die of claim 1 wherein: the substrate materialincludes a silicon wafer; the solid state lighting die further includesa buffer material on the surface of the silicon wafer, the buffermaterial including at least one of aluminum nitride (AlN), galliumnitride (GaN), and zinc nitride (ZnN); the plurality of emitters arearranged in an array; the first semiconductor element includes an N-typeGaN material; the second semiconductor element includes a P-type GaNmaterial; the active element includes GaN/InGaN multiple quantum wells;the second semiconductor element has a semiconductor surface; theinsulating material has an insulating surface generally coplanar withthe semiconductor surface; and the solid state lighting die furtherincludes a conductive material in direct contact with both thesemiconductor surface and the insulating surface.
 4. The solid statelighting die of claim 1 wherein the individual emitters have a size thatis sufficiently small to produce quantum confinement of electrons in theindividual emitters.
 5. The solid state lighting die of claim 1 wherein:the plurality of emitters are arranged in an array; the plurality ofemitters have a generally rectangular cross section with a length L anda width W; the length L is from about 10 nanometers to about 50nanometers; and the width W is from about 10 nanometers to about 50nanometers.
 6. The solid state lighting die of claim 1 wherein: theplurality of emitters are arranged in an array; the plurality ofemitters have a generally rectangular cross section with a length L anda width W; at least one of the emitter has a length L and/or a width Wdifferent than other emitters in the array.
 7. The solid state lightingdie of claim 1 wherein: the plurality of emitters are arranged in anarray; and the emitters have generally the same size, shape, andcomposition.
 8. The solid state lighting die of claim 1 wherein: atleast one of the emitters has a characteristic that is different thanthe other emitters, the characteristic including at least one of a size,shape, and composition of the first semiconductor element, activeelement, and the second semiconductor element.
 9. The solid statelighting die of claim 1 wherein: the emitters include a first group ofemitters that are configured to produce a first emission at a first peakfrequency; the emitters also include a second group of emittersconfigured to produce a second emission at a second peak frequency; andthe first and second emissions in combination at least approximatewhite.
 10. The solid state lighting die of claim 1 wherein: the emittersinclude a first group of emitters having a first characteristic; theemitters also include a second group of emitters having a secondcharacteristic that is different than the first characteristic; and thefirst and second emissions in combination at least approximate white.11. The solid state lighting die of claim 1 wherein: the emittersinclude a first group of emitters having a first characteristic; theemitters also include a second group of emitters having a secondcharacteristic that is different than the first characteristic; thefirst and second characteristics include at least one of a size, shape,and composition of the first semiconductor element, active element, andthe second semiconductor element; and the first and second emissions incombination at least approximate white.
 12. The solid state lighting dieof claim 1, further comprising a buffer material between the pluralityof emitters and the substrate material.
 13. A solid state lighting die,comprising: a substrate material; a first semiconductor material on thesubstrate material; a second semiconductor material spaced apart fromthe first semiconductor material; an active region between the first andsecond semiconductor materials; and a plurality of openings extendingfrom a surface of the second semiconductor material toward the substratematerial through the active region.
 14. The solid state lighting die ofclaim 13 wherein: the plurality of openings are individually between twoadjacent portions of the second semiconductor material and the activeregion; and the portions of the active region individually have a sizethat is sufficiently small to produce quantum confinement of electronsin the portions of the active region.
 15. The solid state lighting dieof claim 13 wherein the plurality of openings individually extend fromthe surface of the second semiconductor material into the active regionwithout extending into the first semiconductor material.
 16. The solidstate lighting die of claim 13 wherein: the solid state lighting diefurther includes a buffer material on the surface of the silicon wafer,the buffer material including at least one of aluminum nitride (AlN),gallium nitride (GaN), and zinc nitride (ZnN); the first semiconductormaterial is in direct contact with the buffer material; and theplurality of openings individually extend from the surface of the secondsemiconductor material into the first semiconductor material withoutextending into the buffer material.
 17. The solid state lighting die ofclaim 13 wherein: the solid state lighting die further includes a buffermaterial on the surface of the silicon wafer, the buffer materialincluding at least one of aluminum nitride (AlN), gallium nitride (GaN),and zinc nitride (ZnN); the first semiconductor material is in directcontact with the buffer material; and the plurality of openingsindividually extend from the surface of the second semiconductormaterial into the buffer material.
 18. The solid state lighting die ofclaim 13 wherein: the solid state lighting die further includes a buffermaterial on the surface of the silicon wafer, the buffer materialincluding at least one of aluminum nitride (AlN), gallium nitride (GaN),and zinc nitride (ZnN); the first semiconductor material is in directcontact with the buffer material; and the plurality of openingsindividually extend from the surface of the second semiconductormaterial into the substrate material via the buffer material.
 19. Amethod for forming a solid state lighting die, comprising: forming afirst semiconductor material, an active region, and a secondsemiconductor material on a substrate material in sequence; depositing amasking material onto the surface of the second semiconductor material;patterning the masking material to define a plurality of openings thatindividually expose a portion of a surface of the second semiconductormaterial; and removing material from at least the second semiconductormaterial and the active region via the plurality of openings.
 20. Themethod of claim 19 wherein removing material includes removing materialfrom the second semiconductor material, the active region, and at leastpartially from the first semiconductor material via the plurality ofopenings.
 21. The method of claim 19 wherein: the method furtherincludes forming a buffer material on the substrate material; formingthe first semiconductor material includes forming the firstsemiconductor material on the buffer material; and removing materialincludes removing material from the second semiconductor material, theactive region, and at least partially from the first semiconductormaterial via the plurality of openings without removing material fromthe buffer material.
 22. The method of claim 19 wherein: the methodfurther includes forming a buffer material on the substrate material;forming the first semiconductor material includes forming the firstsemiconductor material on the buffer material; and removing materialincludes removing material from the second semiconductor material, theactive region, the first semiconductor material, and at least partiallyfrom the buffer material via the plurality of openings.
 23. The methodof claim 19 wherein: the method further includes forming a buffermaterial on the substrate material; forming the first semiconductormaterial includes forming the first semiconductor material on the buffermaterial; and removing material includes removing material from thesecond semiconductor material, the active region, the firstsemiconductor material, the buffer material, and at least partially fromthe substrate material via the plurality of openings.
 24. The method ofclaim 19 wherein: forming the first semiconductor material includesforming the first semiconductor material, the active region, and thesecond semiconductor material on the substrate material; the formedfirst semiconductor material, active region, and second semiconductormaterial include an indentation defect extending from the surface of thesecond semiconductor material toward the substrate material; andremoving material includes removing at least a part of the indentationdefect from the first semiconductor material, the active region, and/orthe second semiconductor material.
 25. The method of claim 19 wherein:forming the first semiconductor material includes forming the firstsemiconductor material, the active region, and the second semiconductormaterial on the substrate material; removing material includes forming aplurality of solid state lighting elements separated from one another bythe individual openings, one of the solid state lighting elementsincluding a threading dislocation extending between the first and secondsemiconductor materials; and the method further includes electricallyisolating the threading dislocation from neighboring solid statelighting elements.
 26. The method of claim 19 wherein: forming the firstsemiconductor material includes forming the first semiconductormaterial, the active region, and the second semiconductor material onthe substrate material; removing material includes forming a pluralityof solid state lighting elements separated from one another by theindividual openings; and the method further includes depositing aninsulating material into the openings.
 27. A method for forming a solidstate lighting die, comprising: forming a masking material on asubstrate material, the masking material including a plurality ofopenings individually exposing a portion of the substrate material; andforming an active region on the exposed portions of the substratematerial, the active region including at least one of (a) indium galliumnitride single quantum well, (b) gallium nitride (GaN)/indium galliumnitride (InGaN) multiple quantum wells, and (c) an InGaN bulk material.28. The method of claim 27 wherein forming the masking material includesforming the masking material on a surface of the substrate material, themasking material including the plurality of openings individuallyexposing a portion of the surface of the substrate material and having asize that is sufficiently small to produce quantum confinement ofelectrons in the formed active region.
 29. The method of claim 27wherein forming an active region includes forming a plurality of activeelements separated from one another by a space.
 30. The method of claim27 wherein: forming an active region includes forming a plurality ofactive elements separated from one another by a space; and the methodfurther includes electrically insulating the active elements from oneanother.
 31. The method of claim 27 wherein: the substrate material hasa substrate surface; the method further includes forming a firstsemiconductor material on the substrate surface of the substratematerial, the first semiconductor material having a semiconductorsurface facing away from the substrate material; and forming the maskingmaterial includes forming the masking material on the semiconductorsurface of the first semiconductor material, the masking materialincluding the plurality of openings individually exposing a portion ofthe semiconductor surface.
 32. The method of claim 27 wherein: thesubstrate material has a substrate surface; the method further includesforming a first semiconductor material on the substrate surface of thesubstrate material, the first semiconductor material having asemiconductor surface facing away from the substrate material; formingthe masking material includes forming the masking material on thesemiconductor surface of the first semiconductor material, the maskingmaterial including the plurality of openings individually exposing aportion of the semiconductor surface; and the method further includesforming the active region on the exposed portions of the semiconductorsurface.
 33. A method for forming a solid state lighting die,comprising: forming a masking material on a substrate material, themasking material including a plurality of openings individually exposinga portion of the substrate material; removing the portion of thesubstrate material via the openings, thereby creating a plurality ofindentations in the substrate material; depositing an insulatingmaterial into the indentations; and thereafter, forming an active regionon the substrate material with the insulating material in theindentations.
 34. The method of claim 33, further comprising removingthe masking material from the substrate material after the insulatingmaterial is deposited into the indentations.
 35. The method of claim 33wherein: the method further comprises removing the masking material fromthe substrate material after the insulating material is deposited intothe indentations; and forming the active region includes forming aplurality of active elements separated from one another by theinsulating material in the indentations.
 36. A solid state lightingdevice, comprising: a support structure; a solid state lighting diedisposed in the support structure; and a converter material on the solidstate lighting die; wherein the solid state lighting die including: afirst semiconductor material; a second semiconductor material spacedapart from the first semiconductor material, the second semiconductormaterial having a surface facing away from the first semiconductormaterial; an active region between the first and second semiconductormaterials; and a plurality of openings extending from the surface of thesecond semiconductor material toward the first semiconductor material.37. The solid state lighting device of claim 36 wherein: the pluralityof openings are individually between two adjacent portions of the secondsemiconductor material and the active region; and the portions of theactive region individually have a size that is sufficiently small toproduce quantum confinement of electrons in the portions of the activeregion.